1. Field of the Invention
The present invention relates to a multi-chip stack package, and more particularly to a multi-chip stack package that can reduce the length of bonding wires.
2. Description of the Related Art
To achieve the small size of the multi-chip package structure, a plurality of chips are stacked on a substrate, and electrically connected to the substrate by wire bonding or flip-chip bonding. Referring to FIG. 1, a conventional multi-chip stack package 100 formed by wire bonding comprises a substrate 110, a first chip 120, a second chip 130, and a plurality of bonding wires 140, 150. The first chip 120 is disposed on the substrate 110, and electrically connected to the substrate 110 through the bonding wires 140. The second chip 130 is stacked on the first chip 120, with a dimension smaller than that of the first chip 120, and electrically connected to the substrate 110 through the bonding wires 150. Since the second chip 130 with a smaller dimension is stacked on the first chip 120, the long bonding wires 150 are required to connect the second chip 130 to the substrate 110. Therefore, when molding, the bonding wires 150 are easily pushed by the mold flow, thus resulting in a short circuit.
Referring to FIG. 2, a multi-chip stack package structure 200 disclosed in the US Pub. No. 2003/0153122 comprises a package substrate 210, a first chip 220, an interposer 230, a second chip 240, and a plurality of bonding wires 250, 260, 270. The package substrate 210 comprises a plurality of bonding pads 211. The first chip 220 comprises a plurality of bonding pads 221, 222 formed on an active surface thereof, and is attached to the package substrate 210 by an adhesive 223. A surface 231 of the interposer 230 is formed with a plurality of bonding pads 232, 233 and a plurality of wires 234 connecting the bonding pads 232 and the bonding pads 233. The interposer 230 is stacked and adhered to the first chip 220 by an adhesive 235, and exposes the bonding pads 221, 222 of the first chip 220. The second chip 240 comprises a plurality of bonding pads 241, and stacked and adhered to the interposer 230 by an adhesive 242. The second chip 240 at least exposes the bonding pads 232, 233 of the interposer 230. The bonding wires 250 are used to connect the bonding pads 241 of the second chip 240 and the bonding pads 232 of the interposer 230. The bonding wires 260 are used to connect the bonding pads 233 of the interposer 230 and the bonding pads 221 of the first chip 220. The bonding wires 270 are used to connect the bonding pads 222 of the first chip 220 and the bonding pads 211 of the substrate 210. Since the wires 234 are used to connect the bonding pads 232 and the bonding pads 233, the second chip 240 can electrically conduct with the substrate 210 through the bonding wires 250, the interposer 230, the bonding wires 260, and the bonding wires 270. However, since the interposer 230 is disposed between the first chip 220 and the second chip 240, the thickness of the stacked chip package is increased.
Consequently, there is an existing need for a multi-chip stack package to solve the above-mentioned problems.